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500 mhz dual integrated dcl with differential drive/receive, level setti ng dacs, and per pin pmu ADATE302-02 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features driver 3-level driver with high-z mode and built-in clamps precision trimmed output resistance low leakage mode (typically <10 na) voltage range: ?2.0 v to +6.0 v 1.0 ns minimum pulse width, 1 v terminated comparator window and differential comparator >1 ghz input equivalent bandwidth load 12 ma maximum current capability per pin pmu force voltage range: ?2.0 v to +6.0 v 5 current ranges: 25 ma, 2 ma, 200 a, 20 a, and 2 a levels 14-bit dac for dcl levels typically <5 mv inl (calibrated) 16-bit dac for pmu levels typically <1.5 mv inl (calibrated) linearity in fv mode hvout output buffer 0 v to 13.5 v output range packages 84-ball, 9 mm 9 mm, flip-chip bga 100-lead tqfp_ep 1.7 w per channel with no load applications automatic test equipment semiconductor test systems board test systems instrumentation and characterization equipment general description the ADATE302-02 is a complete, single-chip solution that performs the pin electronic functions of the driver, the compa- rator, and the active load (dcl), per pin pmu, and dc levels for ate applications. the device also contains an hvout driver with a vhh buffer capable of generating up to 13.5 v. the driver features three active states: data high mode, data low mode, and term mode, as well as an inhibit state. the inhibit state, in conjunction with the integrated dynamic clamp, facilitates the implementation of a high speed active termination. the output voltage range is ?2.0 v to +6.0 v to accommodate a wide variety of test devices. the ADATE302-02 can be used as either a dual single-ended drive/receive channel or a single differential drive/receive channel. each channel of the ADATE302-02 features a high speed window comparator for functional testing as well as a per pin pmu with fv or fi and mv or mi functions. all necessary dc levels for dcl functions are generated by on-chip 14-bit dacs. the per pin pmu features an on-chip 16-bit dac for high accuracy and contains integrated range resistors to minimize external component counts. the ADATE302-02 uses a serial bus to program all functional blocks and has an on-board temperature sensor for monitoring the device temperature.
ADATE302-02 rev. a | page 2 of 58 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 total function ............................................................................... 4 driver ............................................................................................. 5 reflection clamp .......................................................................... 7 normal window comparator .................................................... 7 differential comparator .............................................................. 9 active load .................................................................................. 11 pmu ............................................................................................. 12 external sense (pmus_chx) ................................................... 16 dutgnd input ......................................................................... 17 serial peripheral interface ......................................................... 17 hvout driver ........................................................................... 17 overvoltage detector (ovd) ................................................... 18 16-bit dac monitor mux ......................................................... 19 absolute maximum ratings ......................................................... 20 thermal resistance .................................................................... 20 explanation of test levels ......................................................... 20 esd caution................................................................................ 20 pin configuration and function descriptions ........................... 21 typical performance characteristics ........................................... 27 serial peripheral interface details ................................................ 39 definition of spi word .............................................................. 40 write operation.......................................................................... 41 read operation .......................................................................... 42 reset operation .......................................................................... 43 register map ................................................................................... 44 details of registers ......................................................................... 45 user information ............................................................................ 47 details of dacs vs. levels ......................................................... 48 recommended pmu mode switching sequences ................ 50 block diagrams ............................................................................... 53 outline dimensions ....................................................................... 57 ordering guide .......................................................................... 58 revision history 4/09rev. 0 to rev. a added 100-lead tqfp_ep package ........................... throughout added figure 3, renumbered figures sequentially ................... 22 added table 17, renumbered tables sequentially .................... 22 updated outline dimensions ....................................................... 52 changes to ordering guide .......................................................... 53 6/08revision 0: initial version
ADATE302-02 rev. a | page 3 of 58 functional block diagram 50? 16-bit dac pmu pmu_flag mux * mux * window diff. c * vhh drv 14-bit dac ovd temperature sensor * vol voh c c other channel dut1 force sense r out (trimmed) vch vcl vch vcl iol ioh vcom spi * 100 ? 100? vh vt vl ch1 ch1 dac16_mon measout01 pmus_ch0 data0p data0n rcv0p rcv0n comp_qh0p comp_vtt0 comp_qh0n comp_ql0p tempsense hvout dut0 ovd_ch0 comp_ql0n sdin rst sclk cs sdout ADATE302-02 07278-001 g * mux * one per device. * figure 1. functional block diagram with one of two channels shown
ADATE302-02 rev. a | page 4 of 58 specifications v dd = 10.0 v, v cc = 3.3 v, v ss = ?5.75 v, v plus = 16.75 v, v comp_vttx = 1.5 v, v ref = 5.0 v, v ref_gnd = 0.0 v. all default test conditions are as defined in table 38 . all specified values are at t j = 80c, where t j corresponds to the internal temperature sensor, unless otherwise noted. temperature coefficients are measured at t j = 80c 20c, unless otherwise noted. typical values are based on design, simulation analyses, and/or limited bench evaluations. typical values are not tested or guaranteed. test levels are specified in the explanation of test levels section. total function table 1. parameter min typ max unit test level conditions/comments total function output leakage current pe disable, range e ?20.0 +6.0 +20.0 na p ?2.0 v < v dutx < +6.0 v; pmu and pe disabled via spi; vch = 7.0 v, vcl = ?2.5 v pe disable, range a, b, c, d 7.5 na c t ?2.0 v < v dutx < +6.0 v; pmu and pe disabled via spi; vch = 7.0 v, vcl = ?2.5 v high-z mode ?400 +15 +400 na p ?2.0 v < v dutx < +6.0 v; pmu disabled and pe enabled via spi; rcvx pins active, vch = 7.0 v, vcl = ?2.5v output capacitance 4 pf s vterm mode operation dut pin range ?2.0 +6.0 v d power supplies total supply range, v plus to v ss 22.5 23.25 v d defines psrr conditions vplus supply, v plus 16.25 16.75 17.25 v d defines psrr conditions positive supply, v dd 9.5 10.0 10.5 v d defines psrr conditions negative supply, v ss ?6.0 ?5.75 ?5.5 v d defines psrr conditions logic supply, v cc 3.1 3.3 3.5 v d defines psrr conditions comparator termination, v comp_vttx 1 1.5 3.3 v d v plus supply current, i plus ?1.0 +1.3 +4.0 ma p hvout disabled v plus supply current, i plus 4.0 12.7 17.0 ma p hvout enabled, rcvx pins active, no load, vhh = 12 v logic supply current, i cc 1.0 2.7 10.0 ma p quiescent (spi is static) comparator termination current, i comp_vttx 40.0 46 70.0 ma p positive supply current, i dd 140.0 190 256.0 ma p load power down (ioh = iol = 0 ma) 170.0 231 311.0 ma p load active off (ioh = iol = 12 ma) negative supply current, i ss 200.0 272 406.0 ma p load power down (ioh = iol = 0 ma) 230.0 311 461.0 ma p load active off (ioh = iol = 12 ma) total power dissipation 2.5 3.55 4.0 w p load power down (ioh = iol = 0 ma) 3.0 4.2 5.5 w p load active off (ioh = iol = 12 ma) temperature monitors temperature sensor gain 10 mv/k c t temperature sensor accuracy without calibration over 25c to 100c 6 c c t temperature voltage available on pin a1 at all times and on pin k1 when selected (see table 25 and table 37 ) vref input reference input voltage range for dacs (vref pin) 4.95 5 5.05 v d referenced to v ref_gnd ; not referenced to v dutgnd input bias current 0.08 100 a p tested with 5 v applied
ADATE302-02 rev. a | page 5 of 58 driver vh ? vl 200 mv (to meet dc/ac specifications). table 2. parameter min typ max unit test level conditions/comments dc specifications high-speed differential logic input characteristics (datax, rcvx) input termination resistance 92 100 108 p push 6 ma into xp pins, force 1.3 v on xn pins; measure voltage from xp to xn, calculate resistance (v/i) input voltage differential 0.2 1.0 v p f common-mode voltage 0.85 3.5 v p f input bias current ?20.0 +4.0 +20.0 a p each pin te sted at 2.85 v and 0.35 v, while other high speed pin left open pin output characteristics output high range, vh ?1.9 +6.0 v d output low range, vl ?2.0 +5.9 v d output term range, vt ?2.0 +6.0 v d functional amplitude (vh ? vl) 0.0 8.0 v d am plitude can be programmed to vh = vl, accuracy specifications apply when vh ? vl 200 mv dc output current limit source 75 100 120 ma p driver high, vh = 6.0 v, short dutx pin to ?2.0 v, measure current dc output current limit sink ?120 ?100 ?75 ma p driver low, vl = ?2.0 v, short dutx pin to 6.0 v, measure current output resistance, 50 ma 45.0 48.5 51.0 p source: driver high, vh = 3.0 v, i dutx = 1 ma and 50 ma; sink: driver low, vl = 0.0 v, i dutx = ?1 ma and ?50 ma; v dutx /i dutx absolute accuracy vh tests done with vl = ?2.5 v and vt = ?2.5 v; vl tests done with vh = 7.5 v and vt = 7.5 v; vt tests done with vl = ?2.5 v and vh = 7.5 v; unless otherwise specified vh, vl, vt uncalibrated accuracy ?300 75 +300 mv p e rror measured at calibration points of 0 v and 5 v vh, vl, vt offset tempco 450 v/c c t measured at calibration points vh, vl, vt dnl 1 mv c t after two-point gain/offset calibration vh, vl, vt inl ?10 2.5 +10 mv p after two-point gain/offset cali bration; measured over driver output ranges vh, vl, vt resolution 0.6 1 mv p f after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 0 v and 5 v dutgnd voltage accuracy ?7 1.3 +7 mv p over 0.1 v range; measured at end po ints of vh, vl, and vt functional range vh, vl, vt crosstalk 2 mv c t vl = ?2.0 v: vh = ?1.9 v 6.0 v, vt = ?2.0 v 6.0 v; vh = 6.0 v: vl = ?2.0 v 5.9 v, vt = ?2.0 v 6.0 v; vt = 1.5 v: vl = ?2.0 v 5.9 v, vh = ?1.9 v 6.0 v; dc crosstalk on vl, vh, vt ou tput level when other driver dacs are varied overall voltage accuracy 10 mv c t sum of inl, crosstalk, dutgnd, and tempco over 5c, after gain/offset calibration vh, vl, vt dc psrr 15 mv/v c t measured at calibration points ac specifications rise/fall times toggle datax pins 0.2 v programmed swing 683 ps c b vh = 0.2 v, vl = 0.0 v, terminated; 20% to 80% 1.0 v programmed swing 521 ps c b vh = 1.0 v, vl = 0.0 v, terminated; 20% to 80% 1.8 v programmed swing 430 524 630 ps p/c b vh = 1.8 v, vl = 0.0 v, terminated; 20% to 80% 2.0 v programmed swing 531 ps c b vh = 2.0 v, vl = 0.0 v, terminated; 20% to 80% 3.0 v programmed swing 589 ps c b vh = 3.0 v, vl = 0.0 v, terminated; 20% to 80% 3.0 v programmed swing 811 ps c b vh = 3.0 v, vl = 0.0 v, unterminated; 10% to 90% 5.0 v programmed swing 1105 ps c b vh = 5.0 v, vl = 0.0 v, unterminated; 10% to 90% rise to fall matching 6 ps c b vh = 1.0 v, vl = 0.0 v, terminated; rise to fall within one channel
ADATE302-02 rev. a | page 6 of 58 parameter min typ max unit test level conditions/comments minimum pulse width toggle datax pins 2.0 v programmed swing 1.2 ns c b vh = 2.0 v, vl = 0.0 v, terminated; timing error 27 ps 1.2 ns c b vh = 2.0 v, vl = 0.0 v, terminated; less than 10% amplitude degradation 1.0 ns c b vh = 2.0 v, vl = 0.0 v, terminated; less than 20% amplitude degradation maximum toggle rate 500 mhz c b vh = 2.0 v, vh = 0.0 v, terminated, 18% amplitude degradation dynamic performance, drive (vh to vl and vl to vh) toggle datax pins propagation delay time 2.1 ns c b vh = 2.0 v, vl = 0.0 v, terminated propagation delay tempco 4.5 ps/c c t vh = 1.8 v, vl = 0.0 v, terminated delay matching vh = 2.0 v, vl = 0.0 v, terminated edge to edge 41 ps c b rising vs. falling channel to channel 15 ps c b rising vs. rising, falling vs. falling delay change vs. duty cycle 30 ps c b vh = 3.0 v, vl = 0.0 v, terminated; 5% to 95% duty cycle; 1 mhz overshoot and undershoot 48 mv c b vh = 3.0 v, vl = 0.0 v, terminated settling time (vh to vl) toggle datax pins to within 3% of fina l value 1.2 ns c b vh = 3.0 v, vl = 0.0 v, terminated to within 1% of final value 14 ns c b vh = 3.0 v, vl = 0.0 v, terminated dynamic performance, vterm (vh or vl to vt and vt to vh or vl) toggle rcvx pins propagation delay time 2.7 ns c b vh = 3.0 v, vt = 1.5 v, vl = 0.0 v, terminated delay matching, edge to edge 59 ps c b vh = 3.0 v, vt = 1.5 v, vl = 0. 0 v, terminated; rising vs. falling propagation delay tempco 5.5 ps/c c t vh = 3.0 v, vt = 1.5 v, vl = 0.0 v, terminated transition time, active to vt, vt to active 0.614 ns c b vh = 3.0 v, vt = 1.5 v, vl = 0.0 v, terminated; 20% to 80% dynamic performance, inhibit (vh or vl to/from inhibit) toggle rcvx pins propagation delay time vh = +1.0 v, vl = ?1.0 v, terminated active to inhibit 2.7 ns c b inhibit to active 3.7 ns c b transition time vh = +1.0 v, vl = ?1.0 v, terminated; 20% to 80% active to inhibit 1.3 ns c b inhibit to active 0.4 ns c b i/o spike 157 mv c b vh = 0.0 v, vl = 0.0 v, terminated
ADATE302-02 rev. a | page 7 of 58 reflection clamp clamp accuracy specifications apply when vch > vcl. table 3. parameter min typ max unit test level conditions/comments vch range ?1.0 +6.0 v d uncalibrated accuracy ?200 45 +200 mv p driver high-z, sinking 1 ma; vch error measured at calibration points of 0 v and 5 v resolution 0.6 0.75 mv p f driver high-z, sinking 1 ma ; after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 0 v and 5 v dnl 1 mv c t driver high-z, sinking 1 ma ; after two-point gain/offset calibration inl ?40 2 +40 mv p driver high-z, sin king 1 ma; after two-point gain/offset calibration; measured over vch range of ?1 v to +6 v tempco ?0.5 mv/c c t measured at calibration points vcl range ?2 +5.0 v d uncalibrated accuracy ?200 70 +200 mv p driver high-z, sourcing 1 ma; vcl error measured at calibration points of 0 v and 5 v resolution 0.6 0.75 mv p f driver high-z, sourcing 1 ma ; after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 0 v and 5 v dnl 1 mv c t driver high-z, sourcing 1 ma ; after two-point gain/offset calibration inl ?40 2 +40 mv p driver high-z, sour cing 1 ma; after two-point gain/offset calibration; measured over vcl range of ?2 v to +5 v tempco 0.6 mv/c c t measured at calibration points dc clamp current limit vch ?120 ?83 ?60 ma p driver high-z, vch = 0 v, vcl = ?2.0 v, v dutx = 5 v vcl 60 86 120 ma p driver high-z, vch = 6.0 v, vcl = 5.0 v, v dutx = 0.0 v dutgnd voltage accuracy ?7 1 +7 mv p over 0.1 v range; measured at the end points of vch and vcl functional range normal window comparator voh tests done with vol = ?2.0 v, vol tests done with voh = 6.0 v, unless otherwise specified. table 4. parameter min typ max unit test level conditions/comments dc specifications input voltage range ?2.0 +6.0 v d differential voltage range 0.1 8.0 v d comparator input offset voltage accuracy, uncalibrated ?150 30 +150 mv p offset measured at calibration points of 0 v and 5 v comparator threshold resolution 0.61 1 mv p f after two-point gain/offset calibration; range/ number of dac bits as measured at calibration points of 0 v and 5 v comparator threshold dnl 1 mv c t after two-point gain/offset calibration comparator threshold inl ?7 1.2 +7 mv p afte r two-point gain/offset calibration; measured over voh, vol range of ?2.0 v to +6.0 v comparator input offset voltage tempco 200 v/c c t measured at calibration points
ADATE302-02 rev. a | page 8 of 58 parameter min typ max unit test level conditions/comments dutgnd voltage accuracy ?7 0.5 +7 mv p over 0.1 v range; measured at end points of voh and vol functional range comparator uncertainty range 5.3 mv c b v dutx = 0 v, sweep comparator threshold to determine uncertainty region dc hysteresis 0.5 mv c b v dutx = 0 v dc psrr 5 mv/v c t measured at calibration points digital output characteristics internal pull-up resistance to comparator, comp_vttx pin 46 50 54 p pull 1 ma and 10 ma from logic 1 leg and measure v to calculate resistance; measured v/9 ma; done for both comparator logic states v comp_vttx range 1 1.5 3.3 v d common-mode voltage v comp_vttx ? 0.3 v c t measured with 100 differential termination v comp_vttx ? 0.5 v comp_vttx v p measured with no external termination differential voltage 250 mv c t measured with 100 differential termination 450 500 550 mv p measured wi th no external termination rise/fall time, 20% to 80% 222 ps c b measured with each comparator leg terminated 50 to gnd ac specifications input transition time = 600 ps, 10% to 90%; measured with each comparator leg terminated 50 to gnd; unless otherwise specified propagation delay, input to output 1.4 ns c b v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; high-side meas urement: voh = 0.5 v, vol = ?2.0 v; low-side measurement: voh = 6.0 v, vol = 0.5 v propagation delay tempco 4 ps/c c t v dutx = 0 v to 0.9 v swing, driver vterm mode, vt = 0.0 v; vol = voh = 0.45 v propagation delay matching v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; high-side meas urement: voh = 0.5 v, vol = ?2.0 v; low-side measurement: voh = 6.0 v, vol = 0.5 v high transition to low transition 39 ps c b high to low comparator 30 ps c b propagation delay change with respect to slew rate, 600 ps and 1 ns (10% to 90%) 19 ps c b v dutx = 0 v to 0.5 v swing, driver vterm mode, vt = 0.0 v; high-side meas urement: voh = 0.25 v, vol = ?2.0 v; low-side measurement: voh = 6.0 v, vol = 0.25 v overdrive, 250 mv and 1.0 v 65 ps c b for 250 mv: v dutx = 0 v to 0.5 v swing; for 1.0 v: v dutx = 0 v to 1.25 v swing; driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.25 v, vol = ?2.0 v; low-side measurement: voh = 6.0 v, vol = 0.25 v; input transition time = 400 ps (10%/90%) pulse width, 1 ns, 5 ns, 10 ns, and 15 ns 27 ps c b v dutx = 0 v to 1.0 v swing @ 32.0 mhz, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.5 v, vol = ?2.0 v; low-side measurement: voh = 6.0 v, vol = 0.5 v; input transition time = 400 ps (10%/90%) duty cycle, 5% to 95% 11.8 ps c b v dutx = 0 v to 1.0 v swing @ 1.0 mhz, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.5 v, vol = ?2.0 v; low-side measurement: voh = 6.0 v, vol = 0.5 v; input transition time = 400 ps (10%/90%)
ADATE302-02 rev. a | page 9 of 58 parameter min typ max unit test level conditions/comments minimum pulse width 1 ns c b v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; less than 10% amplitude degradation measured by shmoo; input transition time = 400 ps (10%/90%) input equivalent bandwidth, terminated 1000 mhz c b v dutx = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; as measured by shmoo; input transition time = 400 ps (10%/90%) ert high-z mode, 3 v, 20% to 80% 0.9 ns c b v dutx = 0 v to 3.0 v swing, driver high-z; as measured by shmoo differential comparator voh tests done with vol = ?1.1 v, vol tests done with voh = 1.1 v, unless otherwise specified. table 5. parameter min typ max unit test level conditions/comments dc specifications input voltage range ?1.5 +4.5 v d operational differential voltage range 0.05 1.1 v d maximum differential voltage range 8 v d comparator input offset voltage accuracy, uncalibrated ?150 25 +150 mv p offset measured at differential calibration points of +1 v and ?1 v, with common mode = 0 v voh, vol resolution 0.61 1 mv p f after two-point gain/offset calibration; range/number of dac bits as measured at differential calibration points of +1 v and ?1 v, with common mode = 0 v voh, vol dnl 1 mv c t after two-point gain/offset calibration; common mode = 0 v voh, vol inl ?7 1.0 +7 mv p after two-po int gain/offset calibration; measured over voh, vol range of ?1.1 v to +1.1 v, common mode = 0 v voh, vol offset voltage tempco 200 v/c c t measured at calibration points comparator uncertainty range 18 mv c b v dutx = 0 v, sweep comparator threshold to determine uncertainty region dc hysteresis 0.5 mv c b v dutx = 0 v cmrr 1 mv/v p offset measured at common-mode voltage points of ?1.5 v and +4.5 v, with differential voltage = 0 v dc psrr 15 mv/v c t measured at calibration points ac specifications input transition time = 600 ps, 10% to 90%, measured with each comparator leg terminated 50 to gnd propagation delay, input to output 1.4 ns c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v, vol = 0.0 v; repeat for other dut channel propagation delay tempco 4 ps/c c t v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; vol = voh = 0.0 v; repeat for other dut channel propagation delay matching v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v, vol = 0.0 v; repeat for other dut channel high transition to low transition 27 ps c b high to low comparator 32 ps c b propagation delay change with respect to v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v,
ADATE302-02 rev. a | page 10 of 58 parameter min typ max unit test level conditions/comments vol = 0.0 v; repeat for other dut channel slew rate, 400 ps and 1 ns (10% to 90%) 25 ps c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v, vol = 0.0 v; repeat for other dut channel overdrive, 250 mv and 750 mv 79 ps c b v dut0 = 0 v, for 250 mv: v dut1 = 0 v to 0.5 v swing; for 750 mv: v dut1 = 0 v to 1.0 v swing, driver vterm mode, vt = 0.0 v; voh = ?0.25 v; repeat for other dut channel with comparator threshold = 0.25 v pulse width, 1 ns, 5 ns, 10 ns, and 15 ns 56 ps c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing @ 32 mhz, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v, vol = 0.0 v; repeat for other dut channel duty cycle, 5% to 95% 16 ps c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing @ 32 mhz, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v, vol = 0.0 v; repeat for other dut channel minimum pulse width 1 ns c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v, vol = 0.0 v; less than 22% amplitude degradation measured by shmoo; repeat for other dut channel input equivalent bandwidth, terminated 500 mhz c b v dut0 = 0 v, v dut1 = ?0.5 v to +0.5 v swing, driver vterm mode, vt = 0.0 v; high-side measurement: voh = 0.0 v, vol = ?1.1 v; low-side measurement: voh = 1.1 v, vol = 0.0 v
ADATE302-02 rev. a | page 11 of 58 active load see tabl e 30 for load control information. table 6. parameter min typ max unit test level conditions/comments dc specifications load active on, rcvx pins active, unless otherwise noted input characteristics vcom voltage range ?1.75 +5.75 v d v dutx range ?2.0 +6.0 v d vcom accuracy, uncalibrated ?200 25 +200 mv p ioh = iol = 6 ma, vcom error measured at calibration points of 0 v and 5 v vcom resolution 0.61 1 mv p f ioh = iol = 6 ma, after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 0 v and 5 v vcom dnl 1 mv c t ioh = iol = 6 ma, after two-point gain/offset calibration vcom inl ?7 2 +7 mv p ioh = iol = 6 ma, after two-point gain/offset calibration; measured over vcom range of ?1.75 v to +5.75 v dutgnd voltage accuracy ?7 1 +7 mv p over 0 .1 v range; measured at end points of vcom functional range output characteristics iol maximum source current 12 ma d uncalibrated offset ?600.0 100 +600.0 a p ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, iol offset calculated from calibration points of 1 ma and 11 ma uncalibrated gain ?12 1 +12 % p ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, iol gain calculated from calibration points of 1 ma and 11 ma resolution 1.5 2 a p f ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 1 ma and 11 ma dnl 3.0 a c t ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, after two- point gain/offset calibration inl ?70 20 +70 a p ioh = 0 ma, vcom = 1.5 v, v dutx = 0.0 v, after two- point gain/offset calibration; measured over iol range of 0 ma to 12 ma 90% commutation voltage 0.25 v p ioh = iol = 12 ma, vcom = 2.0 v, measure iol reference at v dutx = ?1.0 v, measure iol current at v dutx = 1.75 v, ensure >90% of reference current ioh maximum sink current 12 ma d uncalibrated offset ?600.0 100 +600.0 a p iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, ioh offset calculated from calibration points of 1 ma and 11 ma uncalibrated gain ?12 1 +12 % p iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, ioh gain calculated from calibration points of 1 ma and 11 ma resolution 1.5 2 a p f iol = 0 ma, vcom = 1.5 v, v dutx = 3.0 v, after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 1 ma and 11 ma dnl 3.0 a c t iol = 0 ma, vcom = 1.5v, v dutx = 3.0 v, after two-point gain/offset calibration inl ?70 20 +70 a p iol = 0 ma, vcom = 1.5v, v dutx = 3.0 v, after two-point gain/offset calibration; measured over ioh range of 0 ma to 12 ma 90% commutation voltage 0.25 v p ioh = iol = 12 ma, vcom = 2.0 v, measure ioh reference at v dutx = 5.0 v, measure ioh current at v dutx = 2.25 v, ensure >90% of reference current output current tempco 1.5 a/c c t measured at calibration points
ADATE302-02 rev. a | page 12 of 58 parameter min typ max unit test level conditions/comments ac specifications load active on, unless otherwise noted dynamic performance propagation delay, load active on to load active off; 50%, 90% 4.1 ns c b toggle rcvx pins, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; measured from 50% point of rcvxp ? rcvxn to 90% point of final output, repeat for drive low and high propagation delay, load active off to load active on; 50%, 90% 11 ns c b toggle rcvx pins, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; measured from 50% point of rcvxp ? rcvxn to 90% point of final output, repeat for drive low and high propagation delay matching 6.9 ns c b toggle rcvx pins, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; active on vs. active off, repeat for drive low and high load spike 156 mv c b toggle rcvx pins, dutx terminated 50 to gnd, ioh = iol = 0 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom = ?1.25 v for ioh; repeat for drive low and high settling time to 90% 1.6 ns c b toggle rcvx pins, dutx terminated 50 to gnd, ioh = iol = 12 ma, vh = vl = 0 v, vcom = +1.25 v for iol and vcom= ?1.25 v for ioh; measured at 90% of final value pmu fv = force voltage, mv = measure voltage, fi = force current, mi = measure current, fn = force nothing. table 7. parameter min typ max unit test level conditions/comments force voltage (fv) current range a 25 ma d current range b 2 ma d current range c 200 a d current range d 20 a d current range e 2 a d force input voltage range at output for all ranges ?2.0 +6.0 v d force voltage uncalibrated accuracy for range c ?100 25 +100 mv p pmu enabled, fv, pe d isabled, error measured at calibration points of 0 v and 5 v force voltage uncalibrated accuracy for all ranges 25 mv c t pmu enabled, fv, pe disabled, error measured at calibration points of 0 v and 5 v; repeat for each pmu current range force voltage offset tempco for all ranges 25 v/c c t measured at calibration points for each pmu current range force voltage gain tempco for all ranges 75 ppm/c c t measured at calibration points for each pmu current range forced voltage inl ?7 2 +7 mv p pmu enabled, fv, range c, pe disabled , after two-point gain/ offset calibration; measured ov er output range of ?2.0 v to +6.0 v force voltage compliance vs. current load pmu enabled, fv, pe disabled, force ?2.0 v, measure voltage while pmu sinking zero- and full-scale current; measure v; force 6.0 v, measure voltage while pmu sourcing zero- and full- scale current; measure v; repeat for each pmu current range range a 4 mv c t range b to range e 1 mv c t
ADATE302-02 rev. a | page 13 of 58 parameter min typ max unit test level conditions/comments current limit, source and sink range a 108 135 180 % fs p pmu enabled, fv, pe disabled; sink: force 2.5 v, short dutx to 6.0 v; source: force 2.5 v, short dutx to ?1.0 v; range a fs = 25 ma, 108% fs = 27 ma, 180% fs = 45 ma range b to range e 120 140 180 % fs p pmu enabled, fv, pe disabled; sink: force 2.5 v, short dutx to 6.0 v; source: force 2.5 v, short dutx to ?1.0 v; repeat for each pmu current range; example: range b fs = 2 ma, 120% fs = 2.4 ma, 180% fs = 3.6 ma dutgnd voltage accuracy ?7 1 +7 mv p over 0.1 v range; measured at end points of fv functional range measure current (mi) v dutx externally forced to 0.0 v, unless otherwise specified; ideal measout transfer functions: v measout01 [v] = (i measout01 5/fsr) + 2.5 + v dutgnd i(v measout01 ) [a] = (v measout01 ? v dutgnd ? 2.5) fsr/5 measure current, pin dutx voltage range for all ranges ?2.0 +6.0 v d measure current uncalibrated accuracy range a 650 a c t pmu enabled, fimi, pe disabled, error at calibration points of ?20 ma and 20 ma, error = (i(v measout01 ) ? i dutx ) range b ?400 20 +400 a p pmu enabled, fimi, pe disabled, error at calibration points of ?1.6 ma and 1.6 ma, error = (i(v measout01 ) ? i dutx ) range c 2.00 a c t pmu enabled, fimi, pe disabled, error at calibration points of 80% fs, error = (i(v measout01 ) ? i dutx ) range d 0.20 a c t pmu enabled, fimi, pe disabled, error at calibration points of 80% fs, error = (i(v measout01 ) ? i dutx ) range e 0.02 a c t pmu enabled, fimi, pe disabled, error at calibration points of 80% fs, error = (i(v measout01 ) ? i dutx ) measure current offset tempco range a 2.5 a/c c t measured at calibration points range b 125 na/c c t measured at calibration points range c 20 na/c c t measured at calibration points range d and range e 4 na/c c t measured at calibration points measure current gain error, nominal gain = 1 range a ?3.5 % c t pmu enabled, fimi, pe disabled, gain error from calibration points of 80% fs range b ?20 2 +20 % p pmu enabled, fimi, pe disabled, gain error from calibration points of 1.6 ma range c to range e 2 % c t pmu enabled, fimi, pe disabled, gain error from calibration points of 80% fs measure current gain tempco measured at calibration points range a 300 ppm/c c t range b to range e 50 ppm/c c t measure current inl range a 0.05 % fsr c t pmu enabled, fimi, pe disabl ed, after two-point gain/offset calibration, measured over fsr output of ?25 ma to +25 ma range b ?0.02 0.005 0.02 % fsr p pmu enabled, fimi, pe disabled, after two-point gain/ offset calibration measured over fsr output of ?2 ma to +2 ma range b to range e 0.005 % fsr c t pmu enabled, fimi, pe disabl ed, after two-point gain/offset calibration; measured over fsr output fvmi dut pin voltage rejection ?0.01 0.01 % fsr/v p pmu en abled, fvmi, pe disabled, force ?1 v and +5 v into load of 1 ma; measure i reported at measout01 dutgnd voltage accuracy 2.5 mv c t over 0.1 v range; measured at end points of mi functional range
ADATE302-02 rev. a | page 14 of 58 parameter min typ max unit test level conditions/comments force current (fi) v dutx externally forced to 0.0 v, unless otherwise specified ideal force current transfer function: i force = (pmudac ? 2.5) (fsr/5) force current, dutx pin voltage range for all ranges ?2.0 +6.0 v d force current uncalibrated accuracy range a ?5.0 0.5 +5.0 ma p pmu enabled, fimi , pe disabled, error at calibration points of ?20 ma and +20 ma range b ?400 40 +400 a p pmu enabled, fimi, pe disabled, error at calibration points of ?1.6 ma and +1.6 ma range c ?40 4 +40 a p pmu enabled, fimi, pe disabled, error at calibration points of 80% fs range d ?4 0.4 +4 a p pmu enabled, fimi, pe disabled, error at calibration points of 80% fs range e ?400 75 +400 na p pmu enabled, fimi, pe disabled, error at calibration points of 80% fs force current offset tempco range a 1 a/c c t measured at calibration points range b 80 na/c c t measured at calibration points range c to range e 4 na/c c t measured at calibration points forced current gain error, nominal gain = 1 ?20 4 +20 % p pmu enabled, fimi, pe disabled, gain error from calibration points of 80% fs forced current gain tempco measured at calibration points range a ?500 ppm/c c t range b to range e 75 ppm/c c t force current inl range a ?0.3 0.05 +0.3 % fsr p pmu enabled, fimi, pe disabled, afte r two-point gain/offset calibration; measured over fsr output of ?25 ma to +25 ma range b to range e -0.2 0.015 0.2 % fsr p pmu enabled, fimi, pe disabled, af ter two-point gain/offset calibration; measured over fsr output force current compliance vs. voltage load pmu enabled, fimv, pe d isabled; force positive full-scale current driving ?2.0 v and +6.0 v, measure i @ dutx pin; force negative full-scale current driving ?2.0 v and +6.0 v, measure i @ dutx pin range a to range d ?0.6 0.06 +0.6 % fsr p range e ?1.0 +0.1 +1.0 % fsr p measure voltage measure voltage range ?2.0 +6.0 v d measure voltage uncalibrated accuracy ?25 2.0 +25 mv p pmu enabled, fvmv, range b, pe disabled, error at calibration points of 0 v and 5 v, error = (v measout01 ? v dutx ) measure voltage offset tempco 10 v/c c t measured at calibration points measure voltage gain error ?2 0.01 +2 % p pmu enab led, fvmv, range b, pe disabled, gain error from calibration points of 0 v and 5 v measure voltage gain te mpco 25 ppm/c c t measured at calibration points measure voltage inl ?7 1 +7 mv p pmu enabled, fvmv, range b, pe disabled, after two-point gain/offset calibration; measured over output range of ?2.0 v to +6.0 v rejection of measure v vs. i dutx ?1.5 0.1 +1.5 mv p pmu enabled, fvmv, range d, pe disabled, force 0 v into load of ?10 a and +10 a; measure v reported at measout01
ADATE302-02 rev. a | page 15 of 58 parameter min typ max unit test level conditions/comments measout01 dc characteristics measout01 voltage range ?2.0 +6.0 v d dc output current 4 ma d measout01 pin output impedance 25 200 p pmu enabled, fvmv, pe disabled; source resistance: pmu force 6.0 v and load with 0 ma and 4 ma; sink resistance: pmu force ?2.0 v and load with 0 ma and ?4 ma; resistance = v/i at measout01 pin output leakage current when tristated ?1 +1 a p tested at ?2.0 v and +6.0 v output short-circuit current ?25 +25 ma p pmu enab led, fvmv, pe disabled; source: pmu force 6.0 v, short measout01 to ?2.0 v; sink: pmu force ?2.0 v, short measout01 to 6.0 v voltage clamps low clamp range (vcl) ?2.0 +4.0 v d high clamp range (vch) 0.0 6.0 v d positive clamp voltage droop ?300 +50 +300 mv p pmu enabled, fimi, range a, pe disabled, pmu clamps enabled, vch = 5 v, vcl = ?1 v, pmu force 1 ma and 25 ma into open; v seen at dutx pin negative clamp voltage droop ?300 ?50 +300 mv p pmu enabled, fimi, range a, pe disabled, pmu clamps enabled, vch = 5 v, vcl = ?1 v, pmu force ?1 ma and ?25 ma into open; v seen at dutx pin uncalibrated accuracy ?250 100 +250 mv p pmu enabled, fimi, range b, pe disabled, pmu damps enabled, pmu force 1 ma into open; vch errors at calibration points of 0 v and 5 v; vcl errors at the calibration points of 0 v and 4 v inl ?70 5 +70 mv p pmu enabled, fimi, range b, pe disabled, pmu damps enabled, pmu force 1 ma into open; after two-point gain/offset calibration; measured over pmu clamp range dutgnd voltage accuracy 1 mv c t over 0.1 v range; measured at end points of pmu clamp functional range settling/switching times scap = 330 pf, ffcap = 220 pf voltage force settling time to 0.1% of final value pmu enabled, fv, pe disabled, program pmudac steps of 500 mv and 5.0 v; simulation of worst case, 2000 pf load, pmudac step of 5.0 v range a, 200 pf and 2000 pf load 15 s s range b, 200 pf and 2000 pf load 20 s s range c, 200 pf and 2000 pf load 124 s s range d, 200 pf and 2000 pf load 1015 s s range e, 200 pf and 2000 pf load 3455 s s voltage force settling time to 1.0% of final value pmu enabled, fv, pe disabled, start with pmudac programmed to 0.0 v, prog ram pmudac to 500 mv range a, 200 pf and 2000 pf load 8.0 s c b range b, 200 pf and 2000 pf load 8.0 s c b range c, 200 pf and 2000 pf load 8.0 s c b range d, 200 pf load 8.1 s c b range d, 2000 pf load 585 s c b range e, 200 pf load 8.1 s c b range e, 2000 pf load 590 s c b
ADATE302-02 rev. a | page 16 of 58 parameter min typ max unit test level conditions/comments voltage force settling time to 1.0% of final value pmu enabled, fv, pe disabled, start with pmudac programmed to 0.0 v, pr ogram pmudac to 5.0 v range a, 200 pf and 2000 pf load 4.2 s c b range b, 200 pf load 4.4 s c b range b, 2000 pf load 7.6 s c b range c, 200 pf load 6.3 s c b range c, 2000 pf load 8.1 s c b range d, 200 pf load 130 s c b range d, 2000 pf load 280 s c b range e, 200 pf load 390 s c b range e, 2000 pf load 605 s c b current force settling time to 0.1% of final value pmu enabled, fi, pe disabled, start with pmudac programmed to 0 current, program pmudac to fs current range a, 200 pf in parallel with 120 8.2 s s range b, 200 pf in parallel with 1.5 k 9.4 s s range c, 200 pf in parallel with 15.0 k 30 s s range d, 200 pf in parallel with 150 k 281 s s range e, 200 pf in parallel with 1.5 m 2668 s s current force settling time to 1.0% of final value pmu enabled, fi, pe disabled, start with pmudac programmed to 0 current, program pmudac to fs current range a, 200 pf in parallel with 120 3.3 s c b range b, 200 pf in parallel with 1.5 k 4.4 s c b range c, 200 pf in parallel with 15.0 k 8 s c b range d, 200 pf in parallel with 150 k 205 s c b range e, 200 pf in parallel with 1.5 m 505 s c b interaction and crosstalk measure voltage channel-to- channel crosstalk 0.125 % fsr c t pmu enabled, fimv, pe disabled, range b, forcing 0 ma into 0 v load; other channel: range a, forcing a step of 0 ma to 25 ma into 0 v load; report v of measout01 pin under test; 0.125% 8.0 v = 10 mv measure current channel-to- channel crosstalk 0.01 % fsr c t pmu enabled, fvmi, pe disabled, range e, forcing 0 v into 0 ma current load; other channel: range e, forcing a step of 0 v to 5 v into 0 ma current load; report v of measout01 pin under test; 0.01% 5.0 v = 0.5 mv external sense (pmus_chx) table 8. parameter min typ max unit test level conditions/comments voltage range ?2.0 +6.0 v d input leakage current ?20 +20 na p tested at ?2.0 v and +6.0 v
ADATE302-02 rev. a | page 17 of 58 dutgnd input table 9. parameter min typ max unit test level conditions/comments input voltage range, referenced to gnd ?0.1 +0.1 v d input bias current 1 100 a p tested at ?100 mv and +100 mv serial peripheral interface table 10. parameter min typ max unit test level conditions/comments serial input logic high 1.8 v cc v p f serial input logic low 0 0.7 v p f input bias current ?10 +1 +10 a p tested at 0.0 v and 3.3 v sclk clock rate 50 mhz p f sclk pulse width 9 ns c t sclk crosstalk on dutx pin 8 mv c b pe disabled, pmu fv enabled and forcing 0 v serial output logic high v cc ? 0.4 v cc v p f sourcing 2 ma serial output logic low 0 0.8 v p f sinking 2 ma update time 10 s d maximum delay time required for the part to enter a stable state after a serial bus command is loaded hvout driver table 11. parameter min typ max unit test level conditions/comments vhh buffer vhh = (vt + 1 v) 2 + dutgnd voltage range 5.9 v plus ? 3.25 v d v plus = 16.75 v nominal; in this condition, v hvout maximum = 13.5 v output high 13.5 v p vhh mode enabled, rcvx pins active, vhh level = full scale, sourcing 15 ma output low 5.9 v p vhh mode enabled, rcvx pins active, vhh level = zero scale, sinking 15 ma accuracy uncalibrated ?500 100 +500 mv p v hh mode enabled, rcvx pins active, v hvout error measured at calibration points of 7 v and 12 v offset tempco 1 mv/c c t measured at calibration points resolution 1.21 1.5 mv p f vhh mode enabled, rcvx pins active, after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 7 v and 12 v inl ?30 15 +30 mv p vhh mode enabled, rcvx pins active, after two-point gain/ offset calibration; measured over vhh range of 5.9 v to 13.5 v dutgnd voltage accuracy 1 mv c t over 0.1 v range; measured at end points of vhh functional range output resistance 1 10 p vhh mode enabled, rcvx pins active, source: vhh = 10.0 v, i hvout = 0 ma and 15 ma; sink: vhh = 6.5 v, i hvout = 0 ma and ?15 ma; v/i dc output current limit source 60 100 ma p vhh mo de enabled, rcvx pins active, vhh = 10.0 v, short hvout pin to 5.9 v, measure current dc output current limit sink ?100 ?60 ma p vhh mo de enabled, rcvx pins active, vhh = 6.5 v, short hvout pin to 14.1 v, measure current rise time (from vl or vh to vhh) 175 ns c b vhh mode enabled, toggle rcvx pins, vhh = 13.5 v, vl = vh = 3.0 v; 20% to 80%, for datax high and datax low
ADATE302-02 rev. a | page 18 of 58 parameter min typ max unit test level conditions/comments fall time (from vhh to vl or vh) 23 ns c b vhh mode enabled, toggle rcvx pins, vhh = 13.5 v, vl = vh = 3.0 v; 20% to 80%, for datax high and datax low preshoot, overshoot, and undershoot 100 mv c b vhh mode enabled, toggle rcvx pins, vhh = 13.5 v, vl = vh = 3.0 v; for datax high and datax low vl/vh buffer voltage range ?0.1 +6.0 v d accuracy uncalibrated ?500 100 +500 mv p vhh mode en abled, rcvx pins inactive, error measured at calibration points of 0 v and 5 v offset tempco 1 mv/c c t measured at calibration points resolution 0.61 0.75 mv p f vhh mode enabled, rcvx pins inactive, after two-point gain/offset calibration; range/number of dac bits as measured at calibration points of 0 v and 5 v inl ?20 4 +20 mv p vhh mode enabled, rcvx pins inactive, after two-point gain/offset calibration; measured over range of ?0.1 v to +6.0 v dutgnd voltage accuracy 2 mv c t over 0.1 v range; measured at end points of vh and vl, functional range output resistance 46 48 50 p vhh mode enable d, rcvx pins inactive, source: vh = 3.0 v, i hvout = 1 ma and 50 ma; sink: vl = 2.0 v, i hvout = ?1 ma and ?50 ma; v/i dc output current limit source 60 100 ma p vhh mo de enabled, rcvx pins inactive, vh = 6.0 v, short hvout pin to ?0.1 v, datax high, measure current dc output current limit sink ?100 ?60 ma p vhh mode enabled, rcvx pins inactive, vl = ?0.1 v, short hvout pin to 6.0 v, datax low, measure current rise time (vl to vh) 10.0 ns c b vhh mode enabled, rcvx pins inactive, vl = 0.0 v, vh = 3.0 v, toggle datax pins; 20% to 80% fall time (vh to vl) 11.3 ns c b vhh mode enabled, rcvx pins inactive, vl = 0.0 v, vh = 3.0 v, toggle datax pins; 20% to 80% preshoot, overshoot, and undershoot 54 mv c b vhh mode enabled, rcv inactive, vl = 0.0 v, vh = 3.0 v, toggle datax pins overvoltage detector (ovd) table 12. parameter min typ max unit test level conditions/comments dc characteristics programmable voltage rang e ?3.0 +7.0 v d accuracy uncalibrated ?200 +200 mv p ovd offset errors measured at programmed levels of 7.0 v and ?3.0 v hysteresis 112 mv c b logic output characteristics off state leakage 10 1000 na p disable ovd alarm, apply 3.3 v to ovd_chx pin, measure leakage current maximum on voltage @100 a 0.2 0.7 v p activa te alarm, force 100 a into ovd_chx, measure active alarm voltage propagation delay 1.8 s c b for ovd high: dutx = 0 v to 6 v swing, ovd_chx high = 3.0 v, ovd_chx low = ?3.0 v; for ovd_chx low: dutx = 0 v to 6 v swing, ovd_chx high = 7.0 v, ovd_chx low = 3.0 v
ADATE302-02 rev. a | page 19 of 58 16-bit dac monitor mux table 13. parameter min typ max unit test level conditions/comments dc characteristics programmable voltage rang e ?2.5 +7.5 v d output resistance 16 k c t pmudac = 0.0 v, fv, i = 0 a, 200 a; v/i
ADATE302-02 rev. a | page 20 of 58 absolute maximum ratings table 14. parameter rating supply voltages positive supply voltage (v dd to gnd) ?0.5 v to +11.0 v positive v cc supply voltage (v cc to gnd) ?0.5 v to +4.0 v negative supply voltage (v ss to gnd) ?6.25 v to +0.5 v supply voltage difference (v dd to v ss ) ?1.0 v to +16.5 v reference ground (dutgnd to gnd) ?0.5 v to +0.5 v agnd to dgnd ?0.5 v to +0.5 v vplus supply voltage (v plus to gnd) ?0.5 v to +17.5 v input voltages input common-mode voltage v ss to v dd short-circuit voltage 1 ?3.0 v to +8.0 v high speed input voltage 2 0 to v cc high speed differential input voltage 3 0 to v cc vref ?0.5 v to +5.5 v dutx i/o pin current dcl maximum short-circuit current 4 140 ma temperature operating temperature, junction 125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 15. thermal resistance package type ja jc unit 84-ball csp_bga 31.1 0.51 c/w explanation of test levels d definition s design verification simulation p 100% production tested p f functionally checked during production test c t characterized on tester c b characterized on bench 1 r l = 0 , v dutx continuous short-circuit condition (vh, vl, vt, high-z, vcom, clamp modes). 2 dataxp, dataxn, rcvxp, rcvxn, under source r = 0 . 3 dataxp to dataxn, rcvxp, rcvxn. 4 r l = 0 , v dutx = ?3 v to +8 v; dcl curre nt limit. continuous short-circuit condition. ADATE302-02 must current limit and survive continuous short circuit. esd caution
ADATE302-02 rev. a | page 21 of 58 pin configurations and function descriptions 07278-002 a b c 1 098765432 1 d e f g h j k hvout pmus_ch0 vsso_0 (drive) dut0 vddo_0 (drive) vddo_1 (drive) dut1 vsso_1 (drive) pmus_ch1 tempsense vplus scap0 vss agnd vdd vdd agnd vss scap1 vdd/vdd_ tmpsns ffcap_0b agnd data0n vss vdd vdd vss data1n agnd ffcap_1b ovd_ch0 vdd data0p data1p vdd ovd_ch1 ffcap_0a vss rcv0n rcv1n vss ffcap_1a agnd agnd rcv0p rcv1p agnd agnd comp_ql0p comp_ql0n comp_vtt0 comp_vtt1 comp_ql1n comp_ql1p comp_qh0p comp_qh0n agnd vss vdd vdd vss agnd comp_qh1n comp_qh1p agnd agnd agnd rst sdin dgnd dac16_mon agnd agnd agnd vref_gnd vref agnd vcc sclk sdout cs agnd dutgnd measout01/ tempsense figure 2. 84-ball bga pin configuration, bottom side (bga balls are visible) table 16. pin function descriptions bga designator mnemonic description a1 tempsense temperature sense output a2 pmus_ch1 pmu external sense path channel 1 a3 vsso_1 (drive) driver output supply ?5.75 v channel 1 a4 dut1 device under test channel 1 a5 vddo_1 (drive) driver output supply +10.0 v channel 1 a6 vddo_0 (drive) driver output supply +10.0 v channel 0 a7 dut0 device under test channel 0 a8 vsso_0 (drive) driver output supply ?5.75 v channel 0 a9 pmus_ch0 pmu external sense path channel 0 a10 hvout high voltage driver output b1 vdd/vdd_tmpsns temperature sense supply +10.0 v b2 scap1 pmu stability capacitor connection channel 1 (330 pf)
ADATE302-02 rev. a | page 22 of 58 bga designator mnemonic description b3 vss supply ?5.75 v b4 agnd analog ground b5 vdd supply +10.0 v b6 vdd supply +10.0 v b7 agnd analog ground b8 vss supply ?5.75 v b9 scap0 pmu stability capacitor connection channel 0 (330 pf) b10 vplus supply +16.75 v c1 ffcap_1b pmu feedforward capacitor connection b channel 1 (220 pf) c2 agnd analog ground c3 data1n driver data input (negative) channel 1 c4 vss supply ?5.75 v c5 vdd supply +10.0 v c6 vdd supply +10.0 v c7 vss supply ?5.75 v c8 data0n driver data input (negative) channel 0 c9 agnd analog ground c10 ffcap_0b pmu feedforward capacitor connection b channel 0 (220 pf) d1 ovd_ch1 overvoltage detection flag output channel 1 d2 vdd supply +10.0 v d3 data1p driver data input (positive) channel 1 d8 data0p driver data input (positive) channel 0 d9 vdd supply +10.0 v d10 ovd_ch0 overvoltage detection flag output channel 0 e1 ffcap_1a pmu feedforward capacitor connection a channel 1 (220 pf) e2 vss supply ?5.75 v e3 rcv1n receive data input (negative) channel 1 e8 rcv0n receive data input (negative) channel 0 e9 vss supply ?5.75 v e10 ffcap_0a pmu feedforward capacitor connection a channel 0 (220 pf) f1 agnd analog ground f2 agnd analog ground f3 rcv1p receive data input (positive) channel 1 f8 rcv0p receive data input (positive) channel 0 f9 agnd analog ground f10 agnd analog ground g1 comp_ql1p low-side comparat or output (positive) channel 1 g2 comp_ql1n low-side comparator output (negative) channel 1 g3 comp_vtt1 comparator supply termination channel 1 g8 comp_vtt0 comparator supply termination channel 0 g9 comp_ql0n low-side comparator output (negative) channel 0 g10 comp_ql0p low-side comparator output (positive) channel 0 h1 comp_qh1p high-side comparator output (positive) channel 1 h2 comp_qh1n high-side comparator output (negative) channel 1 h3 agnd analog ground h4 vss supply ?5.75 v h5 vdd supply +10.0 v h6 vdd supply +10.0 v h7 vss supply ?5.75 v h8 agnd analog ground
ADATE302-02 rev. a | page 23 of 58 bga designator mnemonic description h9 comp_qh0n high-side comparator output (negative) channel 0 h10 comp_qh0p high-side comparator output (positive) channel 0 j1 agnd analog ground j2 agnd analog ground j3 agnd analog ground j4 dac16_mon 16-bit dac monitor mux output j5 dgnd digital ground j6 sdin serial peripheral interface (spi) data in j7 rst serial peripheral interface (spi) reset j8 agnd analog ground j9 agnd analog ground j10 agnd analog ground k1 measout01/tempsense muxed output shared by pmu measout channel 0, pmu measout channel 1, temperature sense and temperature sense gnd reference k2 dutgnd dut ground reference k3 agnd analog ground k4 cs serial peripheral interface (spi) chip select k5 sdout serial peripheral interface (spi) data out k6 sclk serial peripheral interface (spi) clock k7 vcc supply +3.3 v k8 agnd analog ground k9 vref +5 v dac reference voltage k10 vref_gnd dac ground reference
ADATE302-02 rev. a | page 24 of 58 pin 1 ADATE302-02 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 7677 787980 8182 83 848586 87 88 89 90 9192 93 9495 96 9798 99 100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 07278-002 nc nc agnd agnd agnd comp_qh1n comp_qh1p comp_vtt1 comp_ql1n comp_ql1p agnd rcv1p rcv1n vss ffcap_1a data1p data1n ovd_ch1 vdd ffcap_1b scap1 v dd/vdd_tmpsns tempsense nc nc nc nc agnd agnd agnd comp_qh0n comp_qh0p comp_vtt0 comp_ql0n comp_ql0p agnd rcv0p rcv0n vss ffcap_0a data0p data0n ovd_ch0 vdd ffcap_0b scap0 vplus hvout nc nc nc nc pmus_ch0 vss vdd vsso_0 (drive) dut0 vddo_0 (drive) agnd agnd vss vdd agnd vdd vss agnd agnd vddo_1 (drive) dut1 vsso_1 (drive) vdd vss pmus_ch1 nc nc nc nc vref_gnd vref agnd agnd agnd rst vss vcc vdd sdin sclk sdout dgnd vdd vss dac16_mon cs agnd agnd dutgnd measout01/temp sense nc nc notes 1. nc = no connect. 2. exposed pad is connec ted to v ss . figure 3. 100-lead tqfp_ep pin configuration table 17. pin function descriptions pin no. mnemonic description 1 nc no connect. no physic al connection to die. 2 nc no connect. no physic al connection to die. 3 tempsense temperature sense output. 4 vdd/vdd_tmpsns tempera ture sense supply +10.0 v. 5 scap1 pmu stability capacitor connection channel 1 (330 pf). 6 ffcap_1b pmu feed forward capacito r connection b channel 1 (220 pf). 7 vdd supply +10.0 v. 8 ovd_ch1 overvoltage detect ion flag output channel 1. 9 data1n driver data input (negative) channel 1. 10 data1p driver data input (positive) channel 1. 11 ffcap_1a pmu feedforward capacito r connection a channel 1 (220 pf). 12 vss supply ?5.75 v.
ADATE302-02 rev. a | page 25 of 58 pin no. mnemonic description 13 rcv1n receive data input (negative) channel 1. 14 rcv1p receive data input (positive) channel 1. 15 agnd analog ground. 16 comp_ql1p low-side comparator output (positive) channel 1. 17 comp_ql1n low-side comparator output (negative) channel 1. 18 comp_vtt1 comparator supply channel 1. 19 comp_qh1p high-side comparator output (positive) channel 1. 20 comp_qh1n high-side comparator output (negative) channel 1. 21 agnd analog ground. 22 agnd analog ground. 23 agnd analog ground. 24 nc no connect. no phys ical connection to die. 25 nc no connect. no phys ical connection to die. 26 nc no connect. no phys ical connection to die. 27 nc no connect. no phys ical connection to die. 28 measout01/temp sense shared muxed output. muxe d output shared by pmu measout channel 0, pmu measout channel 1, and the temperature sense and temperature sense gnd reference. 29 dutgnd device under test ground reference. 30 agnd analog ground. 31 agnd analog ground. 32 cs serial peripheral interface (spi?) chip select. 33 dac16_mon 16-bit dac monitor mux output. 34 vss supply ? 5.75 v. 35 vdd supply +10.0 v. 36 dgnd digital ground. 37 sdout serial programmable interface (spi) data output. 38 sclk serial programmable interface (spi) clock. 39 sdin serial programmable interface (spi) data input. 40 vdd supply +10.0 v. 41 vcc supply +3.3 v. 42 vss supply ? 5.75 v. 43 rst serial peripheral interface (spi) reset. 44 agnd analog ground. 45 agnd analog ground. 46 agnd analog ground. 47 vref +5 v dac reference voltage. 48 vref_gnd dac ground reference. 49 nc no connect. no physic al connection to die. 50 nc no connect. no physic al connection to die. 51 nc no connect. no physic al connection to die. 52 nc no connect. no physic al connection to die. 53 agnd analog ground. 54 agnd analog ground. 55 agnd analog ground. 56 comp_qh0n high-side comparator output (negative) channel 0. 57 comp_qh0p high-side comparator output (positive) channel 0. 58 comp_vtt0 comparator supply channel 0. 59 comp_ql0n low-side comparator output (negative) channel 0. 60 comp_ql0p low-side comparator output (positive) channel 0.
ADATE302-02 rev. a | page 26 of 58 pin no. mnemonic description 61 agnd analog ground. 62 rcv0p receive data input (positive) channel 0. 63 rcv0n receive data input (negative) channel 0. 64 vss supply ? 5.75 v. 65 ffcap_0a pmu feedforward capacito r connection a channel 0 (220 pf). 66 data0p driver data input (positive) channel 0. 67 data0n driver data input (negative) channel 0. 68 ovd_ch0 overvoltage detect ion flag output channel 0. 69 vdd supply +10.0 v. 70 ffcap_0b pmu feedforward capacito r connection b channel 0 (220 pf). 71 scap0 pmu stability capacitor connection channel 0 (330 pf). 72 vplus supply +16.75 v. 73 hvout high voltage driver output. 74 nc no connect. no physic al connection to die. 75 nc no connect. no physic al connection to die. 76 nc no connect. no physic al connection to die. 77 nc no connect. no physic al connection to die. 78 pmus_ch0 pmu external sense path channel 0. 79 vss supply ? 5.75 v. 80 vdd supply +10.0 v. 81 vsso_0 (drive) driver output supply ? 5.75 v channel 0. 82 dut0 device under test channel 0. 83 vddo_0 (drive) driver outp ut supply +10.0 v channel 0. 84 agnd analog ground. 85 agnd analog ground. 86 vss supply ? 5.75 v. 87 vdd supply +10.0 v. 88 agnd analog ground. 89 vdd supply +10.0 v. 90 vss supply ? 5.75 v. 91 agnd analog ground. 92 agnd analog ground. 93 vddo_1 (drive) driver outp ut supply +10.0 v channel 1. 94 dut1 device under test channel 1. 95 vsso_1 (drive) driver output supply ? 5.75 v channel 1. 96 vdd supply +10.0 v. 97 vss supply ? 5.75 v. 98 pmus_ch1 pmu external sense path channel 1. 99 nc no connect. no physic al connection to die. 100 nc no connect. no physic al connection to die. ep exposed pad. the expose d pad is connected to v ss .
ADATE302-02 rev. a | page 27 of 58 typical performance characteristics 07278-080 time (ns) voltage (v) 0.05 0 0.10 0.15 0.20 0.25 0.30 0.2v 0.5v 024681012141618 07278-085 time (ns) voltage (v) ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2 4 6 8 1012141618 figure 4. driver small signal response; vh = 0.2 v, 0.5 v; vl = 0.0 v; 50 termination figure 7. 100 mhz driver response; vh = 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination 0 7278-084 time (ns) voltage (v) ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 12345678910 0 07278-079 time (ns) voltage (v) ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 2 4 6 8 10 12 14 16 18 figure 8. 300 mhz driver response; vh = 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination figure 5. driver large signal response; vh = 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination 0 7278-078 time (ns) voltage (v) ?1 0 1 2 3 4 5 6 024681012141618 07278-083 time (ns) voltage (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 09 87654321 figure 6. driver large signal response; vh = 1.0 v, 3.0 v, 5.0 v; vl = 0.0 v; 500 termination figure 9. 400 mhz driver response; vh = 0.5 v, 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination
ADATE302-02 rev. a | page 28 of 58 07278-081 time (ns) voltage (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0.51.01.52.02.53.03.54.04.55.0 figure 10. 500 mhz driver response; vh = 0.5 v, 1.0 v, 2.0 v, 3.0 v; vl = 0.0 v; 50 termination 0 7278-082 voltage (v) time (ns) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 figure 11. 600 mhz driver response; vh = 0.5 v, 1.0 v, 2.0 v; vl = 0.0 v; 50 termination 07278-075 time (ns) voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 024681012141618 figure 12. driver active (vh/ vl) to/from vterm transition; vh = 1.0 v; vt = 0.5 v; vl = 0.0 v 0 7278-076 voltage (v) ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 time (ns) 201816141210 86420 figure 13. driver active (vh/ vl) to/from vterm transition; vh = 2.0 v; vt = 1.0 v; vl = 0.0 v 07278-077 voltage (v) time (ns) 2018 16 1412 10 86420 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 figure 14. driver active (vh/ vl) to/from vterm transition; vh = 3.0 v; vt = 1.5 v; vl = 0.0 v ?50 ?40 ?30 ?20 ?10 0 10 11 07278-063 pulse width (ns) trailing edge error (ps) 0 negative pulse positive pulse figure 15. driver minimum pulse width; vh = 0.2 v; vl = 0.0 v
ADATE302-02 rev. a | page 29 of 58 ?50 ?40 ?30 ?20 ?10 0 10 11 0 07278-064 pulse width (ns) trailing edge error (ps) negative pulse positive pulse figure 16. driver minimum pulse width; vh = 0.5 v; vl = 0.0 v 11 0 ?30 ?20 ?10 0 10 07278-065 pulse width (ns) trailing edge error (ps) negative pulse positive pulse figure 17. driver minimum pulse width; vh = 1.0 v; vl = 0.0 v 11 0 ?30 ?20 ?10 0 10 07278-066 pulse width (ns) trailing edge error (ps) negative pulse positive pulse figure 18. driver minimum pulse width; vh = 2.0 v; vl = 0.0 v 11 0 ?50 ?40 ?30 ?20 ?10 0 10 07278-067 pulse width (ns) trailing edge error (ps) negative pulse positive pulse figure 19. driver minimum pulse width; vh = 3.0 v; vl = 0.0 v ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?2 ?1 0 1 2 3 4 56 07278-020 driver output voltage (v) linearity error (mv) figure 20. driver vh linearity error ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?2 ?1 0 1 2 3 4 56 0 7278-021 driver output voltage (v) linearity error (mv) figure 21. driver vl linearity error
ADATE302-02 rev. a | page 30 of 58 ?2?10123456 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 7278-022 driver output voltage (v) linearity error (mv) figure 22. driver vt linearity error ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?2 ?1 0 1 2 3 4 56 0 7278-023 programmed vl dac level (v) interaction error (mv) figure 23. driver interaction error; vh = 6.0 v; vl swept from ?2.0 v to +5.9 v ?2?10123456 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 07278-024 programmed vh dac level (v) interaction error (mv) figure 24. driver interaction error; vt = 1.5 v; vh swept from ?1.9 v to +6.0 v ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 ?2 ?1 0 1 2 3 4 56 0 7278-025 programmed vh dac level (v) interaction error (mv) figure 25. driver interaction error; vl = ?2.0 v; vh swept from ?1.9 v to +6.0 v 47 48 49 50 51 52 53 ?60 ?40 ?20 0 20 40 60 07278-026 driver output current (ma) driver output resistance ( ? ) figure 26. driver output resistance vs. output current ?2 ?1 0 1 2 3 4 56 07278-027 v dutx (v) driver output current (ma) 0 20 40 60 80 100 120 figure 27. driver output current limit; driver programmed to ?2.0 v; v dutx swept from ?2.0 v to +6.0 v
ADATE302-02 rev. a | page 31 of 58 ?2?10123456 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 07278-028 v dutx (v) driver output current (ma) figure 28. driver output current limit; driver programmed to 6.0 v; v dutx swept from ?2.0 v to +6.0 v 07278-086 time (s) voltage (v) 0 2 4 6 8 10 12 14 16 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 figure 29. hvout vhh response; vhh = 13.5 v ?3 ?4 ?2 ?1 0 1 2 3 0123456 07278-037 vl programmed voltage (v) linearity error (mv) figure 30. hvout vl linearity error ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 6 7 8 9 10 11 12 13 14 07278-038 vhh programmed voltage (v) linearity error (mv) figure 31. hvout vhh linearity error 0 10 20 30 40 50 60 70 80 90 ?1 0 1 2 3 4 56 07278-040 v hvout (v) hvout driver current (ma) figure 32. hvout vh current limit; vh = ?0.1 v; v hvout swept from ?0.1 v to +6.0 v ?80 ?60 ?40 ?20 0 20 40 60 80 100 5 6 7 8 9 10 11 12 13 14 15 07278-041 v hvout (v) hvout driver current (ma) figure 33. hvout vhh current limit; vhh = 10.0 v; v hvout swept from 5.9 v to 14.1 v
ADATE302-02 rev. a | page 32 of 58 07278-089 time (ns) voltage (v) 0 1.2 2.4 3.6 4.8 6.0 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 shmoo input edge figure 34. comparator shmoo; 1.0 v swing; 200 ps (10%/90%) 0 7278-090 time (ns) voltage (v) 0 1.2 2.4 3.6 4.8 6.0 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 shmoo input edge figure 35. comparator shmoo; 1.0 v swing; 200 ps (10%/90%) 07278-091 pulse width (ns) trailing edge error (ps) 11 0 ?30 ?20 ?10 0 10 positive pulse negative pulse figure 36. comparator minimum pulse width input; 1.0 v swing; 200 ps (10%/90%) 07278-087 input slew rate [10%/90%] (ns) propagation delay variation (ps) 0 5 10 15 20 25 30 0 . 40 . 60 . 81 . 0 input rising edge input voltage swing = 1v comparator threshold = 0.5v input falling edge figure 37.comparator slew rate dispersion 07278-088 time (ns) voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 1.38 2.76 4.14 5.52 6.90 8.28 9.66 11.00 12.40 13.80 15.20 16.60 17.90 19.30 comp_qh0n comp_qh0p figure 38. comparator output waveform; comp_qh0p, comp_qh0n ?2?10123456 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0 7278-029 program threshold voltage (v) linearity error (mv) figure 39. comparator threshold linearity
ADATE302-02 rev. a | page 33 of 58 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 ?2 ?1 0 1 2 3 45 0 7278-030 input common-mode voltage (v) differential comparator offset (mv) figure 40. differential comparator cmrr 07278-092 time (ns) load current (ma) 0 102030405 3 0 ?3 ?6 ?9 ?12 ?15 0 driver active low (vl) to/from full load current full load currentto/from driver active low (vl) figure 41. active load response ?2?10123456 ?15 ?10 ?5 0 5 10 15 07278-031 v dutx (v) load current (ma) figure 42. active load commutation response; vcom = 2.0 v; ioh = iol = 12 ma ?6 ?4 ?2 0 2 4 6 8 0 2 4 6 8 10 12 0 7278-032 active load current (ma) linearity error (a) figure 43. active load current linearity ?2?10123456 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 07278-033 vcom voltage (v) linearity error (mv) figure 44. active load vcom linearity 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ?2?10123456 07278-034 v dutx (v) i dutx (na) figure 45. dutx pin leakage current in low leakage mode
ADATE302-02 rev. a | page 34 of 58 ?6 ?4 ?2 0 2 4 6 ?2 ?1 0 1 2 3 4 56 07278-035 v dutx (v) i dutx (na) figure 46. dutx pin leakage current in high-z mode ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 07278-039 dutgnd voltage (mv) error voltage (mv) figure 47. dutgnd voltage effects ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 ?3 ?2 ?1 0 1 2 3 4 5 67 0 7278-042 pmu output voltage (v) linearity error (mv) figure 48. pmu force voltage linearity ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 ?30 ?20 ?10 0 10 20 30 07278-043 pmu output current (ma) linearity error (a) figure 49. pmu force current range a linearity ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 07278-044 pmu output current (ma) linearity error (a) figure 50. pmu force current range b linearity ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 07278-045 pmu output current (ma) linearity error (a) figure 51. pmu force current range c linearity
ADATE302-02 rev. a | page 35 of 58 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0 7278-046 pmu output current (ma) linearity error (a) figure 52. pmu force current range d linearity ?0.0008 ?0.0006 ?0.0004 ?0.0002 0 0.0002 0.0004 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 07278-047 pmu output current (ma) linearity error (a) figure 53. pmu force current range e linearity ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 07278-048 i dutx (ma) pmu voltage error (mv) figure 54. pmu force voltage range b output voltage error at 6.0 v vs. output current ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 07278-049 i dutx (ma) pmu voltage error (mv) figure 55. pmu force voltage range b output voltage error at ?2.0 v vs. output current ?4 ?3 ?2 ?1 0 1 2 3 4 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 07278-050 i dutx (ma) pmu voltage error (mv) figure 56. pmu force voltage range a output voltage error at 6.0 v vs. output current ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ?4 ?3 ?2 ?1 0 1 2 3 4 07278-051 i dutx (ma) pmu voltage error (mv) figure 57. pmu force voltage range a output voltage error at ?2.0 v vs. output current
ADATE302-02 rev. a | page 36 of 58 ?10 ?8 ?6 ?4 ?2 0 2 07278-052 v dutx (v) pmu current error (a) ?2?10123456 figure 58. pmu force current range a output current error at ?25 ma vs. output voltage ?60 ?50 ?40 ?30 ?20 ?10 0 10 07278-053 v dutx (v) pmu current error (a) ?2?10123456 figure 59. pmu force current range a output current error at 25 ma vs. output voltage; output voltage is pulled externally ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 07278-054 v dutx (v) pmu current error (a) ?2?10123456 figure 60. pmu force current range b output current error at ?2 ma vs. output voltage; output voltage is pulled externally ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?2 ?1 0 1 2 3 4 56 07278-055 v dutx (v) pmu current error (a) figure 61. pmu force current range b output current error at 2 ma vs. output voltage; output voltage is pulled externally ?2?10123456 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 07278-056 v dutx (v) pmu current error (a) figure 62. pmu force current range e output current error at ?2 a vs. output voltage; output voltage is pulled externally ?2?10123456 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0.0035 07278-057 v dutx (v) pmu current error (a) figure 63. pmu force current range e output current error at 2 a vs. output voltage; output voltage is pulled externally
ADATE302-02 rev. a | page 37 of 58 ?2?10123456 ?40 ?30 ?20 ?10 0 10 20 30 40 07278-058 v dutx (v) pmu current (ma) figure 64. pmu range a internal current limit, programmed to force 2.5 v; v dutx swept from ?2.0 v to +6.0 v ?2?10123456 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 07278-059 v dutx (v) pmu current (ma) figure 65. pmu range e internal current limit, programmed to force 2.5 v; v dutx swept from ?2.0 v to +6.0 v ?2?10123456 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 07278-060 v dutx (v) linearity error (mv) figure 66. pmu range b measure voltage linearity ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 07278-061 i dutx (ma) linearity error (a) ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 figure 67. pmu range b measure current linearity 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 ?2?1012345 07278-062 v dutx (v) pmu voltage error (mv) figure 68. pmu measure current cmrr, externally pulling 1 ma, fvmi; error of mi vs. external 1 ma 07278-068 100mv/di v 1ns/div figure 69. eye diagram, 200 mbps, prbs31; vh = 1.0 v; vl = 0.0 v
ADATE302-02 rev. a | page 38 of 58 07278-069 100mv/di v 500ps/div 07278-072 199.5mv/di v 200ps/div figure 70. eye diagram, 400 mbps, prbs31; vh = 1.0 v; vl = 0.0 v figure 73. eye diagram, 800 mbps, prbs31; vh = 2.0 v; vl= 0.0 v 07278-073 100mv/di v 200ps/div 07278-070 199.5mv/di v 500ps/div figure 71. eye diagram, 400 mbps, prbs31; vh = 2.0 v; vl = 0.0 v figure 74. eye diagram, 1000 mbps, prbs31; vh = 1.0 v; vl = 0.0 v 07278-071 100mv/di v 200ps/div 07278-074 199.5mv/di v 200ps/div figure 72. eye diagram, 800 mbps, prbs31; vh = 1.0 v; vl = 0.0 v figure 75. eye diagram, 1000 mbps, prbs31; vh = 2.0 v; vl = 0.0 v
ADATE302-02 rev. a | page 39 of 58 serial peripheral interface details 07278-003 sclk cs sdin t ch t cl t cssa t csha t cshd t cssd t dh t ds t csw sdout do_2 last do_12 last do_13 last do_14 last do_15 last do_1 last do_0 last t do data[14] data[15] ch[1] r/w addr[1] addr[0] figure 76. spi timing diagram table 18. serial peripheral interface timing requirements smbol parameter min max unit t ch sclk minimum high 9.0 ns t cl sclk minimum low 9.0 ns t csha cs assert hold 3.0 ns t cssa cs assert setup 3.0 ns t cshd cs deassert hold 3.0 ns t cssd cs deassert setup 3.0 ns t dh sdin hold 3.0 ns t ds sdin setup 3.0 ns t do sdout data out 15.0 ns t csw cs minimum between assertions 1 2 sclk cycles cs minimum directly after a read request 3 sclk cycles t cstp minimum delay after cs is deasserted before sclk can be stopped (not shown in ); this allows any internal operations to complete figure 76 16 sclk cycles 1 extra cycle is needed after read request to prime read data into spi shift register.
ADATE302-02 rev. a | page 40 of 58 definition of spi word the spi can take variable length words, depending on the operation. at most, the word is 24 bits longs: 16 bits of data, two ch annel selects, one r/w selector, and a 5-bit address. depending on the operation, the data can be smaller (or nonexistent in the case of a read operation). example 1 write 16 bits of data to a register or dac; unused msbs are ignored. for example, bit 15 and bit 14 are ignored, and bit 13 thr ough bit 0 are applied to the 14-bit dac. 07278-004 data[15:0] ch[1:0] r/w addr[4:0] figure 77. example 2 write 14 bits of data to the dac. 07278-00 5 data[13:0] ch[1:0] r/w addr[4:0] figure 78. example 3a write two bits of data to the 2-bit register. 07278-006 data[1:0] ch[1:0] r/w addr[4:0] figure 79. example 3b write two bits of data to the 2-bit register. bit 15 through bit 2 are ignored, while bit 1 through bit 0 are applied to the re gister. 07278-007 data[15:0] ch[1:0] r/w addr[4:0] figure 80. example 4 read request and follow with a 2 nd instruction (could be nop) to clock out the data. 07278-008 data[15:0] ch[1:0] r/w addr[4:0] ch[1:0] r/w = 0 addr[4:0] figure 81. table 19. channel selection channel 1 channel 0 channel selected 0 0 nop (no channel selected, no register changes) 0 1 channel 0 selected 1 0 channel 1 selected 1 1 channel 0 and channel 1 selected table 20. r/w definition r/w description 0 current register specified by address is shifted out of sdout on next shift operation 1 current data is written to register specified by address and channel select
ADATE302-02 rev. a | page 41 of 58 write operation 07278-009 0 232221 20 191817 16 151413 12 24 25 r/w = 1 data[15] data[14] data[13] data[2] data[1] data[0] ch[ 1] ch[ 0] addr[4] addr[3] addr[2] addr[1] addr[0] x r/w sclk input sdin input cs input sdout output x figure 82. 16-bit spi write 07278-010 0 11 10 987654 123 data[1] data[0] ch[1] ch[0] addr[4] addr[3] addr[2] addr[1] addr[0] r/w r/w = 1 sclk input sdin input sdout output x x cs input figure 83. 2-bit spi write
ADATE302-02 rev. a | page 42 of 58 read operation the read operation is a two-stage operation. first, a word is shifted in, specifying which register to read. cs is deasserted for three clock cycles, and then a second word is shifted in to get the readback data. this second word can be either another operation or an nop address. if another operation is shifted in, it needs to shift in at least eight bits of data to read back the previous specified data. the nop address can be used for this read if there is no need to write/read another register. it is strongly recommended that the nop address be used for all reads for clarity of operations. any register read that is less than 16 bits has zeros filled in the top bits to make it a 16-bit word. 07278-011 x x read instruction nop x read data x sclk input sdin input sdout output cs input figure 84. spi read overview 0 7278-012 x data[15:0], value is a don?t care 0 25 24 23 22 21 20 19 1817 16 15 1413 12 ch[1] x r/w ch[0] addr[4] addr[3] addr[2] addr[1] addr[0] sclk input sdin input sdout output cs input figure 85. spi readdetails of read request 07278-013 x data[15:0], value is a don?t care 0 25 24 23 22 21 20 19 1817 16 15 14 13 12 ch[1] rdata is the register value being read. rdata[15] rdata[2] rdata[1] rdata[0] rdata[14] x r/w = 1 addr[4:0] = 0x00 (nop) ch[0] sclk input sdin input sdout output cs input figure 86. spi readdetails of read out
ADATE302-02 rev. a | page 43 of 58 reset operation the ADATE302-02 contains an asynchronous reset feature. the ADATE302-02 can be reset to the default values shown in tabl e 21 by utilizing the rst pin. to initiate the reset operation, deassert the rst pin for a minimum of 100 ns and deassert the cs pin for a minimum of two sclk cycles. 07278-093 rst cs scl k 100ns minimum minimum of two sclk edges after asserting rst before resuming normal operation. figure 87. reset operation
ADATE302-02 rev. a | page 44 of 58 register map the addr[4:0] bits determine the destination regist er of the data being written to the ADATE302-02. table 21. register selection data[15:0] ch[1:0] r/w addr[4:0] register selected reset state n/a n/a n/a 0x00 nop n/a data[13:0] ch[1:0] r/w 0x01 vh dac level 4096d data[13:0] ch[1:0] r/w 0x02 vl dac level 4096d data[13:0] ch[1:0] r/w 0x03 vt/vcom dac level 4096d data[13:0] ch[1:0] r/w 0x04 vol dac level 4096d data[13:0] ch[1:0] r/w 0x05 voh dac level 4096d data[13:0] ch[1:0] r/w 0x06 vch dac level 4096d data[13:0] ch[1:0] r/w 0x07 vcl dac level 4096d data[13:0] ch[1:0] r/w 0x08 v(ioh ) dac level 4096d data[13:0] ch[1:0] r/w 0x09 v(iol ) dac level 4096d data[13:0] ch[1] r/w 0x0a ovd high level 4096d data[13:0] ch[0] r/w 0x0a ovd low level 4096d data[15:0] ch[1:0] r/w 0x0b pmudac level 16384d data[2:0] ch[1:0] r/w 0x0c pe/pmu enable 000b data[2:0] ch[1:0] r/w 0x0d channel state 000b data[9:0] ch[1:0] r/w 0x0e pmu state 0d data[2:0] ch[1:0] r/w 0x0f pmu measure enable 000b data[0] ch[1:0] r/w 0x10 differential comparator enable 0b data[1:0] ch[1:0] r/w 0x11 16-bit dac monitor 00b data[1:0] ch[1:0] r/w 0x12 ovd_chx alarm mask 01b data[2:0] ch[1:0] r 0x13 ovd_chx alarm state n/a n/a n/a n/a 0x14 to 0x1f reserved n/a
ADATE302-02 rev. a | page 45 of 58 details of registers table 22. pe/pmu enab le (addr[4:0] = 0x0c) bit name description data[2] pmu enable 0 = disable pmu force output and clamps, place pmu in mv mode 1 = enable pmu force output when set to 0, the pmu state bits are ignored, except for pmu sense path (data[7]). data[1] force vt 0 = normal driver operation 1 = force driver to v t see table 30 for complete functionality of this bit. data[0] pe disable 0 = enable driver functions 1 = disable driver (low leakage) see table 30 for complete functionality of this bit. table 23. channel state (addr[4:0] = 0x0d) bit name description data[2] hvout mode select 0 = hvout driver in low impedance 1 = enable hvout driver this bit affects channel 0 only. ensure that channel 0 bit in spi write is active. channel 1 bit in spi write is dont care. data[1] load enable 0 = disable load 1 = enable load see table 30 for complete functionality of this bit. data[0] driver high-z/vt 0 = enable driver high-z function 1 = enable driver vterm function see table 30 for complete functionality of this bit. table 24. pmu state (addr[4:0] = 0x0e) 1 , 2 bit name description data[9:8] pmu input selection 00 = v dutgnd (calibrated for 0.0 v voltage reference) 01 = 2.5 v + v dutgnd (calibrated for 0.0 a current reference) 1x = pmudac data[7] pmu sense path 0 = internal sense 1 = external sense data[6] reserved data[5] pmu clamp enable 0 = disable clamps 1 = enable clamps data[4] pmu measure v/i 0 = measure voltage mode 1 = measure current mode data[3] pmu force v/i 0 = force voltage mode 1 = force current mode data[2:0] pmu range 0xx = range e (2 a) 100 = range d (20 a) 101 = range c (200 a) 110 = range b (2 ma) 111 = range a (25 ma) 1 note that when the addr[4:0] = 0x0c pmu enable bit (data[2]) = 0, the pmu force outputs and cl amps are disabled, and the pmu i s placed into measure voltage mode. data[9:8] and data[6:0] of the pmu state register are ig nored, and only data[7], the pmu sense path bit, is valid. 2 x = dont care.
ADATE302-02 rev. a | page 46 of 58 table 25. pmu measure enable (addr[4:0] = 0x0f) 1 bit name description data[2:1] measout01 select 00 = pmu measout channel 0 01 = pmu measout channel 1 10 = temp sensor ground reference 11 = temp sensor data[0] measout01 output enable 0 = measout01 is tristated 1 = measout01 is enabled 1 this register is written to or read from if either of the ch[1:0] bits is 1. table 26. differential comparat or enable (addr[4:0] = 0x10) 1 bit name description data[0] differential comparator enable 0 = differential compar ator is disabled, channel 0 normal window comparator (nwc) outputs are on channel 0 1 = differential comparator is enabled, the di fferential comparator outputs are on channel 0 1 this register is written to or read from if either of the ch[1:0] bits is 1. table 27. dac16_mon (16-bit dac monitor) (addr[4:0] = 0x11) 1 bit name description data[1] 16-bit dac mux enable 0 = 16-bit dac mux is tristated 1 = 16-bit dac mux is enabled data[0] 16-bit dac mux select 0 = 16-bit dac channel 0 1 = 16-bit dac channel 1 1 this register is written to or read from if either of the ch[1:0] bits is 1. table 28. ovd_chx alarm mask (addr[4:0] = 0x12) bit name description data[1] pmu mask 0 = disable pmu alarm flag 1 = enable pmu alarm flag data[0] ovd mask 0 = disable ovd alarm flag 1 = enable ovd alarm flag table 29. ovd_chx alarm state (addr[4:0] = 0x13) 1 bit name description data[2] pmu clamp flag 0 = pmu not clamped 1 = pmu clamped data[1] ovd high flag 0 = dut voltage < ovd high voltage 1 = dut voltage > ovd high voltage data[0] ovd low flag 0 = dut voltage > ovd low voltage 1 = dut voltage < ovd low voltage 1 this register is a read-only register.
ADATE302-02 rev. a | page 47 of 58 user information table 30. driver and load truth table 1 registers signals driver state load state pe disable data[0] addr[4:0] = 0x0c force vt data[1] addr[4:0] = 0x0c load enable data[1] addr[4:0] = 0x0d driver high-z/vt data[0] addr[4:0] = 0x0d datax rcvx 1 x x x x x high-z without clamps power-down 0 1 x x x x vt power-down 0 0 0 0 0 0 vl power-down 0 0 0 0 0 1 high-z with clamps power-down 0 0 0 0 1 0 vh power-down 0 0 0 0 1 1 high-z with clamps power-down 0 0 0 1 0 0 vl power-down 0 0 0 1 0 1 vt power-down 0 0 0 1 1 0 vh power-down 0 0 0 1 1 1 vt power-down 0 0 1 0 0 0 vl active off 0 0 1 0 0 1 high-z with clamps active on 0 0 1 0 1 0 vh active off 0 0 1 0 1 1 high-z with clamps active on 0 0 1 1 0 0 vl active on 0 0 1 1 0 1 high-z with clamps active on 0 0 1 1 1 0 vh active on 0 0 1 1 1 1 high-z with clamps active on 1 x = dont care. table 31. hvout truth table 1 hvout mode select data[2] addr[4:0] = 0x0d channel 0 rcv channel 0 data hvout driver output 1 1 x vhh mode; vhh = (vt + 1 v) 2 + dutgnd (channel 0 vt dac) 1 0 0 vl (channel 0 vl dac) 1 0 1 vh (channel 0 vh dac) 0 x x disabled (hvout pin set to 0 v low impedance) 1 x = dont care. table 32. comparator truth table differential comparator enable data[0] addr[4:0] = 0x10 comp_qh0 comp_ql0 comp_qh1 comp_ql1 0 normal window mode logic high: voh0 < v dut0 logic low: voh0 > v dut0 normal window mode logic high: vol0 < v dut0 logic low: vol0 > v dut0 normal window mode logic high: voh1 < v dut1 logic low: voh1 > v dut1 normal window mode logic high: vol1 < v dut1 logic low: vol1 > v dut1 1 differential comparator mode logic high: voh0 < v dut0 ? v dut1 logic low: voh0 > v dut0 ? v dut1 differential comparator mode logic high: vol0 < v dut0 ? v dut1 logic low: vol0 > v dut0 ? v dut1 normal window mode logic high: voh1 < v dut1 logic low: voh1 > v dut1 normal window mode logic high: vol1 < v dut1 logic low: vol1 > v dut1
ADATE302-02 rev. a | page 48 of 58 details of dacs vs. levels t here are ten 14-bit dacs per channel. these dacs provide levels for the driver, comparator, load currents, vhh buffer, ovd, and clamp levels. there are three versions of output levels: ? ?2.5 v to +7.5 v; tracks dutgnd. controls vh, vl, vt/vcom/vhh, voh, vol, vch, and vcl levels. ? ?3.0 v to +7.0 v; tracks dutgnd. controls ovd levels. ? ?2.5 v to +7.5 v; does not track dutgnd. controls ioh and iol levels. t here is one 16-bit dac per channel. this dac provides the levels for the pmu. the output level is: ? ?2.5 v to +7.5 v; tracks dutgnd. controls pmu levels. table 33. level transfer functions dac transfer function programmable range 1 (all 0s to all 1s) levels v out = 2.0 (v ref ? v ref_gnd ) (code/(2 14 )) ? 0.5 (v ref ? v ref_gnd ) + v dutgnd code = [v out ? v dutgnd + 0.5 (v ref ? v ref_gnd )] [(2 14 )/(2.0 (v ref ? v ref_gnd ))] ?2.5 v to +7.5 v vh, vl, vt/vcom, vol, voh, vch, vcl v out = 4.0 (v ref ? v ref_gnd ) (code/(2 14 )) ? 1.0 (v ref ? v ref_gnd ) + 2.0 + v dutgnd code = [v out ? v dutgnd ? 2.0 + 1.0 (v ref ? v ref_gnd )] [(2 14 )/(4.0 (v ref ? v ref_gnd ))] ?3.0 v to +17.0 v vhh v out = 2.0 (v ref ? v ref_gnd ) (code/(2 14 )) ? 0.6 (v ref ? v ref_gnd ) + v dutgnd code = [v out ? v dutgnd + 0.6 (v ref ? v ref_gnd )] [(2 14 )/(2.0 (v ref ? v ref_gnd ))] ?3.0 v to +7.0 v ovd i out = [2.0 (v ref ? v ref_gnd ) (code/(2 14 )) ? 0.5 (v ref ? v ref_gnd )] (0.012/5.0) code = [(i out (5.0/0.012)) + 0.5 (v ref ? v ref_gnd )] [(2 14 )/(2.0 (v ref ? v ref_gnd ))] ?6 ma to +18 ma ioh, iol v out = 2.0 (v ref ? v ref_gnd ) (code/(2 16 )) ? 0.5 (v ref ? v ref_gnd ) + v dutgnd code = [v out ? v dutgnd + 0.5 (v ref ? v ref_gnd )] [(2 16 )/(2.0 (v ref ? v ref_gnd ))] ?2.5 v to +7.5 v pmudac i out = [2.0 (v ref ? v ref_gnd ) (code/(2 16 )) ? 0.5 (v ref ? v ref_gnd ) ? 2.5] (0.050/5.0) code = [(i out (5.0/0.050)) + 2.5 + 0.5 (v ref ? v ref_gnd )] [(2 16 )/(2.0 (v ref ? v ref_gnd ))] ?50 ma to +50 ma pmudac (pmu fi range a) i out = [2.0 (v ref ? v ref_gnd ) (code/(2 16 )) ? 0.5 (v ref ? v ref_gnd ) ? 2.5] (0.004/5.0) code = [(i out (5.0/0.004)) + 2.5 + 0.5 (v ref ? v ref_gnd )] [(2 16 )/(2.0 (v ref ? v ref_gnd ))] ?4 ma to +4 ma pmudac (pmu fi range b) i out = [2.0 (v ref ? v ref_gnd ) (code/(2 16 )) ? 0.5 (v ref ? v ref_gnd ) ? 2.5] (0.0004/5.0) code = [(i out (5.0/0.0004)) + 2.5 + 0.5 (v ref ? v ref_gnd )] [(2 16 )/(2.0 (v ref ? v ref_gnd ))] ?400 a to +400 a pmudac (pmu fi range c) i out = [2.0 (v ref ? v ref_gnd ) (code/(2 16 )) ? 0.5 (v ref ? v ref_gnd ) ? 2.5] (0.00004/5.0) code = [(i out (5.0/0.00004)) + 2.5 + 0.5 (v ref ? v ref_gnd )] [(2 16 )/(2.0 (v ref ? v ref_gnd ))] ?40 a to +40 a pmudac (pmu fi range d) i out = [2.0 (v ref ? v ref_gnd ) (code/(2 16 )) ? 0.5 (v ref ? v ref_gnd ) ? 2.5] (0.000004/5.0) code = [(i out (5.0/0.000004)) + 2.5 + 0.5 (v ref ? v ref_gnd )] [(2 16 )/(2.0 (v ref ? v ref_gnd ))] ?4 a to +4 a pmudac (pmu fi range e) 1 programmable range includes margin outside of specified part performance, allowing fo r offset/gain calibration. table 34. load transfer functions load level transfer function 1 iol v(iol)/5 v 12 ma ioh v(ioh)/5 v 12 ma 1 v(ioh), v(iol) dac levels are not referenced to dutgnd. table 35. pmu transfer functions pmu mode transfer function force voltage v out = pmudac measure voltage v measout01 = v dutx (internal sense) or v measout01 = v pmus_chx (external sense) force current i out = [pmudac ? (v ref /2)]/(r 1 5) measure current v measout01 = (v ref /2) + v dutgnd + (i dutx 5 r 1 ) 1 r = 20 for range a; 250 for range b; 2.5 k for range c; 25 k for range d; 250 k for range e.
ADATE302-02 rev. a | page 49 of 58 table 36. pmu user required capacitors capacitor location 220 pf across pin c10 (ffcap_0b) and pin e10 (ffcap_0a) 220 pf across pin c1 (ffcap _1b) and pin e1 (ffcap_1a) 330 pf between gnd and pin b9 (scap0) 330 pf between gnd and pin b2 (scap1) table 37. temperature sensor temperature output 0 k 0 v 300 k 3 v x k (x k) 10 mv/k table 38. default test conditions name default test condition vh dac level 2.0 v vl dac level 0.0 v vt/vcom dac level 1.0 v vol dac level ?2.0 v voh dac level 6.0 v vch dac level 7.5 v vcl dac level ?2.5 v ioh dac level 0.0 a iol dac level 0.0 a ovd low dac level ?2.5 v ovd high dac level 6.5 v pmudac dac level 0.0 v pe/pmu enable 0x0000: pmu disabled, not force vt, pe enabled channel state 0x0000: hvout mode disabled, load disabled, vterm inactive pmu state 0x0000: input of dutgnd, internal sense, clamps disabled, fvmv, range e pmu measure enable 0x0000: measout01 pin tristated differential comparator enable 0x0000: normal window comparator mode 16-bit dac monitor 0x0000: dac16_mon tristated ovd_chx alarm mask 0x0000: disable alarm functions data input logic low receive input logic low dutx pin unterminated comparator output unterminated
ADATE302-02 rev. a | page 50 of 58 recommended pmu mode switching sequences t o minimize any possible aberrations and voltage spikes on the dut output, specific mode switching sequences are recommended fo r the following transitions: ? pmu disable to pmu enable ? pmu force voltage mode to pmu force current mode ? pmu force current mode to pmu force voltage mode. pmu disable to pmu enable step 1: see tabl e 39 for state of registers in pmu disabled mode. table 39. register bit setting pe/pmu enable register, addr[4:0] = 0x0c data[2] 0 pmu state register, addr[4:0] = 0x0e data[9:8] xx data[7] x data[6] x data[5] x data[4] x data[3] x data[2:0] xxx step 2: write to register addr[4:0] = 0x0e (see table 40 ). table 40. register bit setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 1x or 00 set desired input selection data[7] x data[6] x data[5] x data[4] x data[3] 0 this bit must be set to force voltage mode to reduce aberrations data[2:0] xxx set desired range step 3: write to register addr[4:0] = 0x0c (see table 41 ). table 41. register bit setting comments pe/pmu enable register, addr[4:0] = 0x0c data[2] 1 pmu is now enabled in force voltage mode
ADATE302-02 rev. a | page 51 of 58 pmu force voltage mode to pmu force current mode step 1: see tabl e 42 for state of registers in force voltage mode. table 42. register bit setting pe/pmu enable register, addr[4:0] = 0x0c data[2] 1 pmu state register, addr[4:0] = 0x0e data[9:8] xx data[7] x data[6] x data[5] x data[4] x data[3] 0 data[2:0] xxx step 2: write to register addr[4:0] = 0x0e (see table 43 ). table 43. register bit setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 01 set 2.5 v + v dutgnd input selection data[7] x data[6] x data[5] x data[4] x data[3] 1 set to force current mode data[2:0] 0xx 2 a range has the minimum offset current step 3: write to register addr[4:0] = 0x0b (see table 44 ). table 44. register bit setting comments pmudac level, addr[4:0] = 0x0b data[15:0] x update the pmudac level register to the desired value step 4: write to register addr[4:0] = 0x0e (see table 45 ). table 45. register bit setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 1x pmudac input selection data[7] x data[6] x data[5] x data[4] x data[3] 1 set to force current mode data[2:0] xxx set to the desired current range
ADATE302-02 rev. a | page 52 of 58 transition from pmu force current mode to pmu force voltage mode step 1: see tabl e 46 for state of registers in force current mode. table 46. register bits setting pe/pmu enable register, addr[4:0] = 0x0c data[2] 1 pmu state register, addr[4:0] = 0x0e data[9:8] xx data[7] x data[6] x data[5] x data[4] x data[3] 1 data[2:0] xxx step 2: write to register addr[4:0] = 0x0e (see table 47 ). table 47. register bits setting comments pmu state register, addr[4:0] = 0x0e da ta[9:8] 00 set dutgnd input selection data[7] x data[6] x data[5] x data[4] x data[3] 0 set to force voltage mode data[2:0] xxx set to the desired current range step 3: write to register addr[4:0] = 0x0b (see table 48 ). table 48. register bits setting comments pmudac level, addr[4:0] = 0x0b data[15:0] x update the pmudac level register to the desired value step 4: write to register addr[4:0] = 0x0e (see table 49 ). table 49. register bits setting comments pmu state register, addr[4:0] = 0x0e data[9:8] 1x pmudac input selection data[7] x data[6] x data[5] x data[4] x data[3] 0 force voltage mode data[2:0] xxx
ADATE302-02 rev. a | page 53 of 58 block diagrams rcv vt vcl vch data vh vl v(iol) v(ioh) dut driver high-z/vt data[0] (addr[4:0] = 0x0d) vt buffer when 1 high-z buffer when 0 force vt data[1] (addr[4:0] = 0x0c) overrides the rcv pin and forces v term mode on the driver and load power-down mode load enable data[1] (addr[4:0] = 0x0d) forces switches open and powers down load when 0 pe disable data[0] (addr[4:0] = 0x0c) forces switch open when 1 r out = 48 ? (trimmed) driver vcom 07278-014 figure 88. driver and load block diagram 48? vl data rcv (shown in rcv = 0 state) vhh = (vt + 1v) 2 + dutgnd vh ~1 ? hv mode select data[2] (addr [4:0] = 0x0d) disables hv driver and forces 0v on hvout when 0 hvout 07278-015 figure 89. hvout dr iver output stage
ADATE302-02 rev. a | page 54 of 58 07278-016 ? ? ? ? + dut0 ? dut1 2:1 mux differential comparator enable data[0] (addr[4:0] = 0x10) + vol0 v oh0 dut1 dut0? dut1 differential buffer vol0 voh0 vol nwc voh nwc vol dmc voh dmc dut0 comp_qh0 comp_ql0 2:1 mux notes 1. differential comparator only on channel 0. + + figure 90. comparator block diagram 07278-017 comp_vtt 10ma 50 ? 50 ? comp_qp comp_qn figure 91. comparator output scheme
ADATE302-02 rev. a | page 55 of 58 2.5 + dutgnd 10k? 225k ? 2a 20a 200a 2ma 22.5k ? 2.25k ? 250? cra = 220pf ffcap_a ffcap_b mv 20 ? dut ref in-amp g = 5 measout01 select data[2:1] (addr[4:0] = 0x0f) pmu force v/i data[3] (addr[4:0] = 0x0e) pmu input selection data[9:8] (addr[4:0] = 0x0e) pmu clamp enable data[5] (addr[4:0] = 0x0e) pmu sense p a th d a t a [7] (addr[4:0] = 0x0e) external dut sense pin pmu measure v/i data[4] (addr[4:0] = 0x0e) ch[1] pmu v/i mux mux mux mux mux vch vcl measure v (at output of sense mux) notes 1. switches connected with dotted lines represent pmu range data[2:0] (addr[4:0] = 0x0e); when pmu enable d ata[2] = 0 (addr[4:0 ] = 0x0c), all switches open and pmu powers down. 2. the external sense path must close the loop to enable the clamps to operate correctly. 3. 25ma range has its own output buffer. 4. 25ma buffer will be tristated when not in use. 330pf scap (external) 25ma 25ma buffer temp sense gnd ref measure v measure i temp sense vin 2.5v + dutgnd dutgnd measure out measout01 output enable data[0] (addr[4:0] = 0x0f) one per device 07278-018 figure 92. pmu block diagram
ADATE302-02 rev. a | page 56 of 58 pmu v/i clamp flag ?2.5v ovd low level dac (addr[4:0] = 0x0a, ch[0]) (addr[4:0] = 0x12) data[1] pmu mask enables pmu v/i flag to alarm ovd_chx pin ADATE302-02 (addr[4:0] = 0x12) data[0] ovd mask enables ovd flags to alarm ovd_chx pin ovd_chx short circuit current = 100a (addr[4:0] = 0x13) 2 data[2] data[1] data[0] 1 the ovd high/low level dac is shared by each channel; therefore, only one ovd high/low voltage level can be set per chip. the ovd dacs provide a voltage range of ?3v to +7v. the recommended high/low settings are +6.5v/?2.5v. (these values need to be programmed by the user upon startup/reset.) 2 this is a read only register that allows the user to determine the cause of the active ovd flag. 6.5v ovd high level dac (addr[4:0] = 0x0a, ch[1]) dut 1 1 07278-019 figure 93. ovd block diagram
ADATE302-02 rev. a | page 57 of 58 outline dimensions 091108-a * compliant to jedec standards mo-219 with exception to package height. 0.80 bsc a b c d e f g 987654 2 31 bottom view 7.20 bsc sq h j detail a top view detail a coplanarity 0.12 0.90 ref 0.53 0.48 0.43 0.83 0.76 0.69 0.38 0.33 0.28 ball diameter seating plane 9.10 9.00 sq 8.90 a1 ball corner a1 ball corner * 1.20 1.09 1.00 6.731 ref sq k 10 0.305 ref 0.36 ref figure 94. 84-ball chip scale package ball grid array [csp_bga] (bc-84-2) dimensions shown in millimeters compliant to jedec standards ms-026-aed-hu 072408-a 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.75 0.60 0.45 1.20 max 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 0.27 0.22 0.17 0.50 bsc lead pitch 8.00 bsc sq exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 95. 100-lead thin quad flatpack, exposed pad [tqfp_ep] (sv-100-7) dimensions shown in millimeters
ADATE302-02 rev. a | page 58 of 58 ordering guide model temperature range package description package option ADATE302-02bbcz 1 ?40c to +85c 84-ball chip scale package ball grid array [csp_bga] bc-84-2 ADATE302-02bsvz 1 ?40c to +85c 100-lead thin quad fl atpack, exposed pad [tqfp_ep] sv-100-7 1 z = rohs compliant part. ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07278-0-4/09(a)

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